Texas Instruments-NE555DR Standard Timer Single 8-Pin SOIC T/R Print Email

by Kenny Lee Attention electronics

The device NE555DR is a precision timing circuit capable of producing accurate time delay or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger level of the NE555DR normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop of the NE555DR is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate of the NE555DR a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

Parametrics

NE555DR absolute maximum ratings: (1)Case temperature for 60 s FK package 260 ℃; (2)Lead temperature 1, 6 mm (1/16 in) from case for 60 s JG package 300 ℃; (3)Tstg Storage temperature range –65 150 ℃; (4)VCC Supply voltage 18 V; (5)VI Input voltage CONT, RESET, THRES, TRIG VCC V; (6)IO Output current ±225 mA.

Features

NE555DR features: (1)Timing From Microseconds to Hours; (2)Adjustable Duty Cycle; (3)Astable or Monostable Operation; (4)TTL-Compatible Output Can Sink or Source up to 200 mA.

Diagrams